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Automatic microarchitectural pipelining

Author
Galceran, M.; Cortadella, J.; Bufistov, D.; Kishinevsky, M.
Type of activity
Presentation of work at congresses
Name of edition
Design, Automation & Test in Europe 2010
Date of publication
2010
Presentation's date
2010
Book of congress proceedings
Design, Automation & Test in Europe: Dresden, Germany, March 8-12, 2010: proceedings
First page
961
Last page
964
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
10.1109/DATE.2010.5456910
Repository
http://hdl.handle.net/2117/132753 Open in new window
URL
https://ieeexplore.ieee.org/document/5456910 Open in new window
Abstract
This paper presents a method for automatic microarchitectural pipelining of systems with loops. The original specification is pipelined by performing provably-correct transformations including conversion to a synchronous elastic form, early evaluation, inserting empty buffers, anti-tokens, and retiming. The design exploration is done by solving an optimization problem followed by simulation of solutions. The method is explained on a DLX microprocessor example. The impact of different microarchit...
Citation
Galceran, M. [et al.]. Automatic microarchitectural pipelining. A: Design, Automation and Test in Europe Conference and Exhibition. "Design, Automation & Test in Europe: Dresden, Germany, March 8-12, 2010: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 2010, p. 961-964.
Keywords
Clocks, Counting circuits, Delay, Design automation, Design optimization, Microarchitecture, Pipeline processing, Protocols, Space exploration, Wires
Group of research
ALBCOM - Algorithms, Computational Biology, Complexity and Formal Methods

Participants

  • Galceran Oms, Marc  (author and speaker )
  • Cortadella Fortuny, Jordi  (author and speaker )
  • Bufistov, Dmitry  (author and speaker )
  • Kishinevsky, Michael  (author and speaker )

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