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Variable-latency design by function speculation

Author
Baneres, D.; Cortadella, J.; Kishinevsky, M.
Type of activity
Presentation of work at congresses
Name of edition
Design, Automation and Test in Europe 2009
Date of publication
2009
Presentation's date
2009
Book of congress proceedings
Design, Automation and Test in Europe: Nice, France, April 20-24, 2009: proceedings
First page
1704
Last page
1709
DOI
10.1109/DATE.2009.5090937
URL
https://ieeexplore.ieee.org/document/5090937 Open in new window
Abstract
Variable-latency designs may improve the performance of those circuits in which the worst-case delay paths are infrequently activated. Telescopic units emerged as a scheme to automatically synthesize variable-latency circuits. In this paper, a novel approach is proposed that brings three main contributions with regard to the methods used for telescopic units: first, no multi-cycle timing analysis is required to ensure the correctness of the circuit; second, the method can be applied to large cir...
Keywords
Combinational circuits, Logic design, Network synthesis
Group of research
ALBCOM - Algorithms, Computational Biology, Complexity and Formal Methods

Participants

  • Baneres, David  (author and speaker )
  • Cortadella Fortuny, Jordi  (author and speaker )
  • Kishinevsky, Michael  (author and speaker )