Loading...
Loading...

Go to the content (press return)

Light NUCA: a proposal for bridging the inter-cache latency gap

Author
Suárez, D.; Monreal, T.; Vallejo, F.; Viñals, V.; Beivide, J.R.
Type of activity
Presentation of work at congresses
Name of edition
Design, Automation and Test in Europe 2009
Date of publication
2009
Presentation's date
2009-04-22
Book of congress proceedings
Design, Automation and Test in Europe: Nice, France, April 20-24, 2009: proceedings
First page
530
Last page
535
Publisher
IEEE Computer Society
Repository
http://hdl.handle.net/2117/13287 Open in new window
Abstract
To deal with the “memory wall” problem, microprocessors include large secondary on-chip caches. But as these caches enlarge, they originate a new latency gap between them and fast L1 caches (inter-cache latency gap). Recently, Non-Uniform Cache Architectures (NUCAs) have been proposed to sustain the size growth trend of secondary caches that is threatened by wire-delay problems. NUCAs are size-oriented, and they were not conceived to close the inter-cache latency gap. To tackle this problem,...
Citation
Suárez, D. [et al.]. Light NUCA: a proposal for bridging the inter-cache latency gap. A: Design, Automation and Test in Europe. "Design, Automation and Test in Europe 2009". Nice: IEEE Computer Society, 2009, p. 530-535.
Keywords
L-NUCAs, Light NUCAs, NUCAs, Non-uniform cache architectures
Group of research
CAP - High Performace Computing Group

Participants

  • Suárez Gracía, Dario  (author and speaker )
  • Monreal Arnal, Teresa  (author and speaker )
  • Vallejo, Fernando  (author and speaker )
  • Viñals Yufera, Victor  (author and speaker )
  • Beivide Palacio, Julio Ramon  (author and speaker )

Attachments