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LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors

Author
Lira, J.; Molina, C.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
27th IEEE International Conference on Computer Design
Date of publication
2009
Presentation's date
2009-10
Book of congress proceedings
2009 IEEE International Conference on Computer Design: October 4-7, 2009, Resort at Squaw Creek, Lake Tahoe, CA
First page
275
Last page
281
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
https://doi.org/10.1109/ICCD.2009.5413142 Open in new window
Repository
http://hdl.handle.net/2117/101167 Open in new window
URL
http://ieeexplore.ieee.org/document/5413142/ Open in new window
Abstract
The increasing speed-gap between processor and memory and the limited memory bandwidth make last-level cache performance crucial for CMP architectures. non uniform cache architectures (NUCA) have been introduced to deal with this problem. This memory organization divides the whole memory space into smaller pieces or banks allowing nearer banks to have better access latencies than further banks. Moreover, an adaptive replacement policy that efficiently reduces misses in the last-level cache could...
Citation
Lira, J., Molina, C., González, A. LRU-PEA: A smart replacement policy for non-uniform cache architectures on chip multiprocessors. A: IEEE International Conference on Computer Design. "2009 IEEE International Conference on Computer Design: October 4-7, 2009, Resort at Squaw Creek, Lake Tahoe, CA". Lake Tahoe, CA: Institute of Electrical and Electronics Engineers (IEEE), 2009, p. 275-281.
Keywords
Bandwidth, Cache memory, Delay, Energy consumption, Multiprocessor interconnection networks, Performance analysis, Wire
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Lira Rueda, Javier  (author and speaker )
  • Molina Clemente, Carlos  (author and speaker )
  • Gonzalez Colas, Antonio Maria  (author and speaker )

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