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End-to-end register data-flow continuous self-test

Author
Carretero, J.S.; Chaparro, P.; Vera, F.J.; Abella, J.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
The 36th Annual International Symposium on Computer Architecture
Date of publication
2009
Presentation's date
2009
Book of congress proceedings
ISCA '09: proceedings of the 36th annual international symposium on Computer architecture
First page
105
Last page
115
DOI
https://doi.org/10.1145/1555754.1555770 Open in new window
URL
http://dl.acm.org/citation.cfm?id=1555770 Open in new window
Abstract
While Moore's Law predicts the ability of semi-conductor industry to engineer smaller and more efficient transistors and circuits, there are serious issues not contemplated in that law. One concern is the verification effort of modern computing systems, which has grown to dominate the cost of system design. On the other hand, technology scaling leads to burn-in phase out. As a result, in-the-field error rate may increase due to both actual errors and latent defects. Whereas data can be protected...
Keywords
Control logic, Degradation, Design errors, End-to-end protection, Online testing
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Carretero Casado, Javier Sebastian  (author and speaker )
  • Chaparro, Pedro  (author and speaker )
  • Vera Rivera, Francisco Javier  (author and speaker )
  • Abella Ferrer, Jaume  (author and speaker )
  • Gonzalez Colas, Antonio Maria  (author and speaker )