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Using Arm’s scalable vector extension on stencil codes

Author
Armejach, A.; Caminal, H.; Cebrián González, Juan Manuel; Langarita, R.; González-Alberquilla, R.; Adeniyi-Jones, C.; Valero, M.; Casas, M.; Moreto, M.
Type of activity
Journal article
Journal
Journal of supercomputing
Date of publication
2020-03
Volume
76
First page
2039
Last page
2062
DOI
10.1007/s11227-019-02842-5
Project funding
Ajut per a contractació RYC-2016-21104
Computación de Altas Prestaciones VII
Models de programació i entorns d'execució paral·lels
Repository
http://hdl.handle.net/2117/169340 Open in new window
URL
https://link.springer.com/article/10.1007/s11227-019-02842-5 Open in new window
Abstract
Data-level parallelism is frequently ignored or underutilized. Achieved through vector/SIMD capabilities, it can provide substantial performance improvements on top of widely used techniques such as thread-level parallelism. However, manual vectorization is a tedious and costly process that needs to be repeated for each specific instruction set or register size. In addition, automatic compiler vectorization is susceptible to code complexity, and usually limited due to data and control dependenci...
Citation
Armejach, A. [et al.]. Using Arm’s scalable vector extension on stencil codes. "Journal of supercomputing", vol. 76, Març 2020, p. 2039-2062.
Keywords
Data-level parallelism, Scalable vector extension, Stencil computations, Vector-length agnostic
Group of research
CAP - High Performace Computing Group

Participants

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