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Aging in CMOS RF linear power amplifiers: experimental comparison and modeling

Author
Aragones, X.; Mateo, D.; Barajas, E.; Crespo-Yepes, A.; Rodríguez, R.; Martin, J.; Nafría, M.
Type of activity
Presentation of work at congresses
Name of edition
2019 IEEE International Symposium on Circuits and Systems
Date of publication
2019
Presentation's date
2019-05-27
Book of congress proceedings
2019 IEEE International Symposium on Circuits and Systems (ISCAS): proceedings: 26-29 May 2019: Sapporo, Japan
First page
1
Last page
5
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
DOI
10.1109/ISCAS.2019.8702100
Project funding
Multilevel approach to the reliability-aware design of analog and digital integrated circuits
Towards Trusted Low-Power Things: Devices, Circuits and Architectures
Repository
http://hdl.handle.net/2117/143192 Open in new window
URL
https://ieeexplore.ieee.org/document/8702100 Open in new window
Abstract
This paper characterizes experimentally the aging degradation experienced by two different 2.45 GHz power amplifier circuits of similar performance, implemented in a 65 nm CMOS technology. Results demonstrate the importance of the topology selection in order to guarantee robustness against aging effects, and thus the need to predict MOS parameter degradation during the design phase, accounting for the actual DC and RF operation conditions. For that purpose, we propose a semi-empirical compact mo...
Citation
Aragones, X. [et al.]. Aging in CMOS RF linear power amplifiers: experimental comparison and modeling. A: IEEE International Symposium on Circuits and Systems. "2019 IEEE International Symposium on Circuits and Systems (ISCAS): proceedings: 26-29 May 2019: Sapporo, Japan". Institute of Electrical and Electronics Engineers (IEEE), 2019, p. 1-5.
Keywords
Aging, Power amplifier, RF, Reliability
Group of research
HIPICS - High Performance Integrated Circuits and Systems

Participants