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Exploiting task-based programming models for resilience

Author
Jaulmes, L.
Type of activity
Theses
Other related units
Department of Computer Architecture
Defense's date
2019-06-21
URL
http://hdl.handle.net/2117/166153 Open in new window
Abstract
Hardware errors become more common as silicon technologies shrink and become more vulnerable, especially in memory cells, which are the most exposed to errors. Permanent and intermittent faults are caused by manufacturing variability and circuits ageing. While these can be mitigated once they are identified, their continuous rate of appearance throughout the lifetime of memory devices will always cause unexpected errors. In addition, transient faults are caused by effects such as radiation or sm...
Group of research
CAP - High Performace Computing Group
Citation
Jaulmes, L. E. "Exploiting task-based programming models for resilience". Tesi doctoral, UPC, Departament d'Arquitectura de Computadors, 2019.

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