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Postbond test of through-silicon vias with resistive open defects

Author
Rodriguez-Montanes, R.; Arumi, D.; Figueras, J.
Type of activity
Journal article
Journal
IEEE transactions on very large scale integration (VLSI) systems
Date of publication
2019-07-17
First page
1
Last page
12
DOI
10.1109/TVLSI.2019.2925971
Repository
http://hdl.handle.net/2117/169517 Open in new window
URL
https://ieeexplore.ieee.org/document/8765618 Open in new window
Abstract
Through-silicon vias (TSVs) technology has attracted industry interest as a way to achieve high bandwidth, and short interconnect delays in nanometer three-dimensional integrated circuits (3-D ICs). However, TSVs are critical elements susceptible to undergoing defects at steps, such as fabrication and bonding or during their lifetime. Resistive open defects have become one of the most frequent failure mechanisms affecting TSVs. They include microvoids, underfilling, misalignment, pinholes in the...
Keywords
Design for testability, TSV testing., duty cycle (DC), resistive open defect, three-dimensional integrated circuit (3-D IC), through-silicon via (TSV)
Group of research
CRnE - Barcelona Research Center in Multiscale Science and Engineering
QINE - Low Power Design, Test, Verification and Security ICs

Participants