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Implementation of systolic algorithms using pipelined functional units

Author
Valero-Garcia, M; Navarro, J.; Llaberia, J.; Valero, M.
Type of activity
Presentation of work at congresses
Name of edition
International Conference on Application Specific Array Processors 1990
Date of publication
1990
Presentation's date
1990
Book of congress proceedings
Proceedings of the International Conference on Application Specific Array Processors
First page
272
Last page
283
DOI
https://doi.org/10.1109/ASAP.1990.145464 Open in new window
Repository
http://hdl.handle.net/2117/8884 Open in new window
URL
http://ieeexplore.ieee.org/document/145464/ Open in new window
Abstract
The authors present a method to implement systolic algorithms (SAs) using pipelined functional units (PFUs). This kind of unit makes it possible to improve the throughput of a processor because of the possibility of initiating a new operation before the previous one has been completed. The method permits transformation of a SA so that it can be efficiently executed using PFUs. The method is based on two temporal transformations (slowdown and retiming) and one spatial transformation (coalescing)....
Citation
Valero-Garcia, M; Navarro, J.; Llaberia, J.; Valero, M. Implementation of systolic algorithms using pipelined functional units. A: International Conference on Application Specific Array Processors. "Proceedings of the International Conference on Application Specific Array Processors". Institute of Electrical and Electronics Engineers (IEEE), 1990, p. 272-283.
Keywords
Pipeline processing, Systolic arrays
Group of research
CAP - High Performace Computing Group
ICARUS - Intelligent Communications and Avionics for Robust Unmanned Aerial Systems

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