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Systematic design of two-level pipelined systolic arrays with data contraflow

Author
Valero-Garcia, M; Navarro, J.; Llaberia, J.; Valero, M.
Type of activity
Presentation of work at congresses
Name of edition
1988 IEEE International Symposium on Circuits and Systems
Date of publication
1988
Presentation's date
1988
Book of congress proceedings
1988 IEEE International Symposium on Circuits and Systems: proceedings
First page
2521
Last page
2525
DOI
https://doi.org/10.1109/ISCAS.1988.15455 Open in new window
Repository
http://hdl.handle.net/2117/8885 Open in new window
URL
http://ieeexplore.ieee.org/document/15455/ Open in new window
Abstract
Many systolic algorithms and related design methodologies have been recently proposed. Frecuently, in these systolic algorithms practical considerations are not taken into account. Equitatively distributed load between processing elements, pipelined functional units etc, are desirable features when implementing systolic algorithms.In this paper we present a design methodology in which these features are considered. As an example, the methodology is applied to obtain a problem-size-independent, t...
Citation
Valero-García, M; Navarro, J.; Llaberia, J.; Valero, M. Systematic design of two level pipelined systolic arrays with data contraflow. A: IEEE International Symposium on Circuits and Systems. "1988 IEEE International Symposium on Circuits and Systems: proceedings". Institute of Electrical and Electronics Engineers (IEEE), 1988, p. 2521-2525.
Group of research
CAP - High Performace Computing Group
ICARUS - Intelligent Communications and Avionics for Robust Unmanned Aerial Systems

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