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Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies

Author
Barredo, A.; Cebrián González, Juan Manuel; Valero, M.; Casas, M.; Moreto, M.
Type of activity
Journal article
Journal
Journal of supercomputing
Date of publication
2020-03
Volume
76
First page
1960
Last page
1979
DOI
10.1007/s11227-019-02841-6
Repository
http://hdl.handle.net/2117/186274 Open in new window
URL
https://link.springer.com/article/10.1007/s11227-019-02841-6 Open in new window
Abstract
Moore’s Law predicted that the number of transistors on a chip would double approximately every 2 years. However, this trend is arriving at an impasse. Optimizing the usage of the available transistors within the thermal dissipation capabilities of the packaging is a pending topic. Multi-core processors exploit coarse-grain parallelism to improve energy efficiency. Vectorization allows developers to exploit data-level parallelism, operating on several elements per instruction and thus, reducin...
Citation
Barredo, A. [et al.]. Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies. "Journal of supercomputing", Març 2020, vol. 76, p. 1960-1979.
Keywords
DVFS, Efficiency, Power wall, Vector
Group of research
CAP - High Performace Computing Group

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