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Technological layer

Author
Rubio, A.; Canal, R.
Type of activity
Book chapter
Book
Cross-layer reliability of computing systems
First page
3
Last page
22
Publisher
The Institution of Engineering and Technology
Date of publication
2020-10
ISBN
9781785617980
DOI
10.1049/PBCS057E
Repository
http://hdl.handle.net/2117/341025 Open in new window
https://digital-library.theiet.org/content/books/cs/pbcs057e Open in new window
URL
http://www.theiet.org/ Open in new window
Abstract
Reliability has always been a major concern in designing computing systems. However, the increasing complexity of such systems has led to a situation where efforts for assuring reliability have become extremely costly, both for the design of solutions for the mitigation of possible faults, and for the reliability assessment of such techniques. Cross-layer reliability is fast becoming the preferred solution. In a cross-layer resilient system, physical and circuit level techniques can mitigate low...
Citation
Rubio, A.; Canal, R. Technological layer. A: "Cross-layer reliability of computing systems". Londres: The Institution of Engineering and Technology, 2020, p. 3-22.
Keywords
CMOS, DRAM, SRAM, evaluation, manufacturing, memory, reliability, technology nodes
Group of research
HIPICS - High Performance Integrated Circuits and Systems
VIRTUOS - Virtualisation and Operating Systems

Participants