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Tidy Cache: Improving data placement in die-stacked DRAM caches

Author
Armejach, A.; Cristal, A.; Unsal, O.
Type of activity
Presentation of work at congresses
Name of edition
27th International Symposium on Computer Architecture and High-Performance Computing
Date of publication
2015
Presentation's date
2015-10-18
Book of congress proceedings
SBAC-PAD 2015: IEEE 27th International Symposium on Computer Architecture and High Performance Computing: 18-21 October 2015: Florianápolis, Brazil
First page
65
Last page
73
DOI
10.1109/SBAC-PAD.2015.23
Project funding
Computación de Altas Prestaciones VI
URL
https://ieeexplore.ieee.org/document/7379835 Open in new window
Abstract
Die-stacked DRAM caches are likely to become available in mainstream chips in the near future. DRAM caches are typically used as a last level shared cache behind the traditional hierarchy of on-chip SRAM caches. However, its internal organization differs from traditional caches as it is based on DRAM technology that provides significantly diverse access latencies depending on the state of its internal structures. Accesses that hit in the row-buffer require only one DRAM command and are significa...
Keywords
3D stacking, Cache, DRAM
Group of research
CAP - High Performace Computing Group

Participants