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Performance advantages of merging instruction and data-level parallelism

Autor
Quintana, F.; Espasa, R.; Valero, M.
Tipus d'activitat
Document cientificotècnic
Data
1998-10
Codi
UPC-DAC-1998-44
Resum
This report presents a new architecture based on addding a vector pipeline to a superscalar microprocessor. The goal of this report is to show that instruction-level parallelism (ILP) and data-level parallelism (DLP) can be merged in a single architecture to execute regular vectorizable code at a performance level that can not be achieved using only ILP techniques. We present an analysis of the two paradigms at the instruction set architecture (ISA) level that shows that the DLP model has severa...
Paraules clau
Data level parallelism, Instruction level parallelism, Instruction set architecture, Superscalar processors, Vector processors
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants