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Implicit transactional memory in chip multiprocessors

Autor
Galluzzi, M.; Vallejo, E.; Cristal, A.; Vallejo, F.; Beivide, R.; Stenström, P.; Smith, J.; Valero, M.
Tipus d'activitat
Document cientificotècnic
Data
2007-06
Codi
UPC-DAC-RR-CAP-2007-14
Repositori
http://hdl.handle.net/2117/108083 Obrir en finestra nova
Resum
Chip Multiprocessors (CMPs) are an efficient way of designing and use the huge amount of transistors on a chip. Different cores on a chip can compose a shared memory system with a very low-latency interconnect at a very low cost. Unfortunately, consistency models and synchronization styles of popular programming models for multiprocessors impose severe performance losses. Known architectural approaches to combat these losses are too complex, too specialized, or not transparent to the software. I...
Citació
Galluzzi, M., Vallejo, E., Cristal, A., Vallejo, F., Beivide, R., Stenström, P., Smith, J., Valero, M. "Implicit transactional memory in chip multiprocessors". 2007.
Paraules clau
Implicit transaction, Kilo-instruction, Memory consistency, Multiprocessor
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions

Participants

  • Galluzzi, Marco  (autor)
  • Vallejo, Enrique  (autor)
  • Cristal Kestelman, Adrian  (autor)
  • Vallejo, Fernando  (autor)
  • Beivide Palacio, Ramon  (autor)
  • Stenström, Per  (autor)
  • Smith, James E.  (autor)
  • Valero Cortes, Mateo  (autor)

Arxius