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A distributed processor state management architecture for large-window processors

Author
Gonzalez, I.; Galluzzi, M.; Veidenbaum, A.; Ramírez, M.; Cristal, A.; Valero, M.
Type of activity
Report
Date
2008-05
Code
UPC-DAC-RR-CAP-2008-10
Abstract
Processor architectures with large instruction windows have been proposed to expose more instruction-level parallelism (ILP) and increase performance. Some of the proposed architectures replace a re-order buffer (ROB) with a checkpointing mechanism and an out-of-order release of processor resources. Check-pointing, however, leads to an imprecise processor state recovery on mis-predicted branches and exceptions and re-execution of correct-path instructions after state recovery. It also requires ...
Group of research
CAP - High Performace Computing Group

Participants