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Implementing a hybrid SRAM / eDRAM NUCA architecture

Author
Lira, J.; Molina, C.; Brooks, D.; Gonzalez, A.
Type of activity
Report
Date
2010-08-27
Code
UPC-DAC-RR-ARCO-2010-3
Repository
http://hdl.handle.net/2117/13932 Open in new window
Abstract
In this paper, we propose a hybrid cache architecture that exploits the main features of both memory technologies, speed of SRAM and high density of eDRAM. We demonstrate, that due to the high locality found in emerging applications, a high percentage of data that enters to the on-chip last-level cache are not accessed again before they are replaced
Group of research
ARCO - Microarchitecture and Compilers

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