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vPROBE: Variation aware post-silicon power/performance binning using embedded 3T1D cells

Author
Ganapathy, S.; Canal, R.; Gonzalez, A.; Rubio, A.
Type of activity
Report
Date
2010-09-05
Code
UPC-DAC-RR-ARCO-2010-4
Repository
http://hdl.handle.net/2117/13911 Open in new window
Abstract
In this paper, we present an on-die post-silicon binning methodology that takes into account the effect of static and dynamic variations and categorizes every processor based on power/performance.The proposed scheme is composed of a discretization hardware that exploits the delay/leakage dependence on variability sources characteristic for categorization
Group of research
ARCO - Microarchitecture and Compilers
HIPICS - High Performance Integrated Circuits and Systems
VIRTUOS - Virtualisation and Operating Systems

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