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Dynamically optimizing code stream for narrow-bitwidth architectures through local productiveness pruning

Author
Bhagat, I.; Gonzalez, A.
Type of activity
Report
Date
2011-01-26
Code
UPC-DAC-RR-ARCO-2011-1
Abstract
Narrow computations have been unequivocally adopted for multiple incentives -- lowering the hardware-complexity of the processor datapath, enhancing the power-efficiency of the processor, and increasing performance amongst others. In this work, we harness a strictly narrow (16-bit integer datapath), in-order processor design to truly exploit these benefits of narrow computations and to uncover further opportunities. We envision a hardware-software collaborative framework where the hardware is a ...
Group of research
ARCO - Microarchitecture and Compilers

Participants