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Reduced interconnection networks based in the multiple bus for multimicroprocessor systems

Autor
Fiol, M.; Valero, M.; Andrés, J.; Lang, T.
Tipus d'activitat
Article en revista
Revista
International journal of mini and microcomputers
Data de publicació
1984
Volum
6
Número
1
Pàgina inicial
4
Pàgina final
9
Resum
The multiple-bus interconnection network connects the P processors to the M memory modules in a multiprocessor system through B buses, where B¿min{P,M}. This is an attractive alternative solution which yields a throughput between those of the single bus and the crossbar with higher reliability. Recently, several studies have evaluated the bandwidth of the network by various techniques and in various situations. Also, it has been shown that B(B-1) connections, among the B(P+M) which the multiple...
Paraules clau
Computer architecture, Multiprocessing systems, Switching networks
Grup de recerca
CAP - Grup de Computació d'Altes Prestacions
COMBGRAPH - Combinatòria, Teoria de Grafs i Aplicacions

Participants