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A fully-distributed first level memory architecture

Author
Bieschewski, S.; Parcerisa, Joan-Manuel; Gonzalez, A.
Type of activity
Report
Date
2007-10
Code
UPC-DAC-RR-ARCO-2007-3
Abstract
Clustered microarchitectures are a becoming mainstream due to its effectiveness to tackle delays, area and power issues in modern microprocessors. This work presents a novel microarchitecture for a fully- distributed first level memory architecture for clustered microprocessors.
Group of research
ARCO - Microarchitecture and Compilers

Participants