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Conflict-free strides for vectors in matched memories

Author
Valero, M.; Lang, T.; Llaberia, J.; Peiron, M.; Navarro, J.; Ayguade, E.
Type of activity
Journal article
Journal
Parallel processing letters
Date of publication
1991-12
Volume
1
Number
2
First page
95
Last page
102
DOI
https://doi.org/10.1142/S0129626491000045 Open in new window
URL
http://www.worldscientific.com/doi/abs/10.1142/S0129626491000045 Open in new window
Abstract
Address transformation schemes, such as skewing and linear transformations, have been proposed to achieve conflict-free access to one family of strides in vector processors with matched memories. The paper extends these schemes to achieve this conflict-free access for several families. The basic idea is to perform an out-of-order access to vectors of fixed length, equal to that of the vector registers of the processor. The hardware required is similar to that for the access in order.
Keywords
Conflict-free access, Out-of-order access, Parallel memory architectures, Storage schemes, Vector access
Group of research
CAP - High Performace Computing Group

Participants