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Power/performance/thermal design space exploration for multicore architectures

Author
Monchiero, M.; Canal, R.; Gonzalez, A.
Type of activity
Report
Date
2006-08
Code
701
Abstract
This paper presents a thorough evaluation of multicore architectures. The architecture we target is composed of a configurable number of cores, a memory hierarchy consisting of private L1, shared/private L2, and a shared bus interconnect.
Group of research
ARCO - Microarchitecture and Compilers
VIRTUOS - Virtualisation and Operating Systems

Participants