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Bipolar transistor vertical vertical scaling framework

Author
Castañer, L.; Alcubilla, R.; Benavent, A.
Type of activity
Journal article
Journal
Solid-state electronics
Date of publication
1994-12
Volume
38
Number
7
First page
1367
Last page
1371
DOI
10.1016/0038-1101(94)00254-D
Repository
http://hdl.handle.net/2117/131231 Open in new window
URL
https://www.sciencedirect.com/science/article/pii/003811019400254D Open in new window
Abstract
Scaling factors for current and transit time are derived for polysilicon emitter, silicon based heterojunction bipolar transistors. It is shown that a simple set of analytical equations in integral form can be used to analyse the above scaling properties and by introducing two “heterojunction factors” can be extended to the scaling analysis of heterojunction bipolar transistors.
Citation
Castañer, L.; Alcubilla, R.; Benavent, A. Bipolar transistor vertical vertical scaling framework. "Solid-state electronics", Desembre 1994, vol. 38, núm. 7, p. 1367-1371.
Group of research
MNT - Micro and Nanotechnologies Research Group

Participants