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IDDQ-based diagnosis at very low voltage (VLV) for bridging defects

Author
Arumi, D.; Rodriguez-Montanes, R.; Figueras, J.; Eichenberger, S.; Hora, C.; Kruseman, B.; Lousberg, M.
Type of activity
Journal article
Journal
Electronics Letters
Date of publication
2007-03
Volume
43
Number
5
First page
25
Last page
26
DOI
https://doi.org/10.1049/el:20073573 Open in new window
URL
http://ieeexplore.ieee.org/document/4137468/ Open in new window
Abstract
Bridging defects generate two currents related to the fault-free case: bridge current and downstream current. The latter may complicate the diagnosis of bridging defects. However, in CMOS technologies, the downstream current can be minimised at low power supply (VDD) values, thus facilitating the diagnosis of such defects. Experimental evidence of this behaviour is presented
Group of research
CRnE - Barcelona Research Center in Multiscale Science and Engineering
QINE - Low Power Design, Test, Verification and Security ICs

Participants