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Delay caused by resistive opens in interconnecting lines

Author
Arumi, D.; Rodriguez-Montanes, R.; Figueras, J.
Type of activity
Journal article
Journal
Integration. The VLSI journal
Date of publication
2009-06
Volume
42
Number
3
First page
286
Last page
293
DOI
https://doi.org/10.1016/j.vlsi.2008.11.001 Open in new window
URL
http://www.sciencedirect.com/science/article/pii/S0167926008000680 Open in new window
Group of research
CRnE - Barcelona Research Center in Multiscale Science and Engineering
QINE - Low Power Design, Test, Verification and Security ICs

Participants