Loading...
Loading...

Go to the content (press return)

Dynamic code partitioning for clustered architectures

Author
Canal, R.; Parcerisa, Joan-Manuel; Gonzalez, A.
Type of activity
Journal article
Journal
International journal of parallel programming
Date of publication
2001-02
Volume
29
Number
1
First page
59
Last page
79
DOI
https://doi.org/10.1023/A:1026483904675 Open in new window
Abstract
Recent works show that delays introduced in the issue and bypass logic will become critical for wide issue superscalar processors. One of the proposed solutions is clustering the processor core. Clustered architectures benefit from a less complex partitioned processor core and thus, incur less critical delays. We propose a dynamic instruction steering logic for these clustered architectures that decides at decode time the cluster where each instruction is executed. The performance of clustered a...
Keywords
Floating point arithmetic, Formal logic, Instruction sets, Parallel architectures
Group of research
ARCO - Microarchitecture and Compilers
VIRTUOS - Virtualisation and Operating Systems