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Improving latency tolerance of multithreading through decoupling

Author
Parcerisa, Joan-Manuel; Gonzalez, A.
Type of activity
Journal article
Journal
IEEE transactions on computers
Date of publication
2001-10
Volume
50
Number
10
First page
1084
Last page
1094
DOI
https://doi.org/10.1109/12.956093 Open in new window
Repository
http://hdl.handle.net/2117/96788 Open in new window
URL
http://ieeexplore.ieee.org/document/956093/ Open in new window
Abstract
The increasing hardware complexity of dynamically scheduled superscalar processors may compromise the scalability of this organization to make an efficient use of future increases in transistor budget. SMT processors, designed over a superscalar core, are therefore directly concerned by this problem. The article presents and evaluates a novel processor microarchitecture which combines two paradigms: simultaneous multithreading and access/execute decoupling. Since its decoupled units issue instru...
Citation
Parcerisa, Joan-Manuel, González, A. Improving latency tolerance of multithreading through decoupling. "IEEE transactions on computers", Octubre 2001, vol. 50, núm. 10, p. 1084-1094.
Keywords
Access/execute decoupling, Hardware complexity, Instruction-level parallelism, Latency hiding
Group of research
ARCO - Microarchitecture and Compilers

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