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On-chip interconnects and instruction steering schemes for clustered microarchitectures

Author
Parcerisa, Joan-Manuel; Sahuquillo Borrás, Julio; Gonzalez, A.; Duato Marín, José Francisco
Type of activity
Journal article
Journal
IEEE transactions on parallel and distributed systems
Date of publication
2005-02
Volume
16
Number
2
First page
130
Last page
144
DOI
https://doi.org/10.1109/TPDS.2005.23 Open in new window
Repository
http://hdl.handle.net/2117/100490 Open in new window
URL
http://ieeexplore.ieee.org/document/1374854/ Open in new window
Abstract
Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection networks for clustered superscalar microarchitectures. This new class of interconnects has demands and characteristics different from traditional multiprocessor networks. In particular, in a clustered microarchitecture, a low intercluster communication latency is essential ...
Citation
Parcerisa, J.M., Sahuquillo, J., González, A., Duato, J. On-chip interconnects and instruction steering schemes for clustered microarchitectures. "IEEE transactions on parallel and distributed systems", Febrer 2005, vol. 16, núm. 2, p. 130-144.
Keywords
Clustered microarchitecture, Complexity, Instruction steering, Intercluster communication, On-chip interconnects
Group of research
ARCO - Microarchitecture and Compilers

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