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Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability

Autor
Liang, X.; Canal, R.; Wei, G.-Y.
Tipus d'activitat
Article en revista
Revista
IEEE micro
Data de publicació
2008-02
Volum
28
Número
1
Pàgina inicial
60
Pàgina final
68
DOI
https://doi.org/10.1109/MM.2008.12 Obrir en finestra nova
Repositori
http://hdl.handle.net/2117/121204 Obrir en finestra nova
URL
https://ieeexplore.ieee.org/document/4460513/ Obrir en finestra nova
Resum
With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the L1 data cache tolerates wide process variations with little performance degradation, making it a promising choice for on-chip cache structures for next-generation microprocessors.
Citació
Liang, X., Canal, R., Wei, G.-Y. Replacing 6T SRAMs with 3T1D DRAMs in the L1 data cache to combat process variability. "IEEE micro", Febrer 2008, vol. 28, núm. 1, p. 60-68.
Paraules clau
Cache storage, DRAM chips, Microprocessor chips, SRAM chips, System-on-chip, Transistors
Grup de recerca
VIRTUOS - Virtualisation and Operating Systems

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