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A performance and area efficient architecture for intrusion detection systems

Autor
Sreekar Shenoy, G.; Tubella, J.; Gonzalez, A.
Tipus d'activitat
Presentació treball a congrés
Nom de l'edició
25th IEEE International Parallel and Distributed Processing Symposium
Any de l'edició
2011
Data de presentació
2011-05-16
Llibre d'actes
Proceedings: 25th IEEE International Parallel and Distributed Processing Symposium: May 16-20 2011, Anchorage, Alaska, USA
Pàgina inicial
301
Pàgina final
310
DOI
https://doi.org/10.1109/IPDPS.2011.37 Obrir en finestra nova
URL
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6012846 Obrir en finestra nova
Resum
Intrusion Detection Systems (IDS) have emerged as one of the most promising ways to secure systems in network. An IDS operates by scanning packet-data for known signatures and accordingly takes requisite action. However, scanning bytes in the packet payload and checking for more than 20,000 signatures becomes a computationally intensive task. Additionally, with signatures doubling almost every 30 months, this complexity will aggravate further. IDS commonly uses the Aho-Corasick state machine bas...
Paraules clau
Arrays, Databases, Hardware, Pattern matching, Program processors, Proposals
Grup de recerca
ARCO - Microarquitectura i Compiladors

Participants