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Thread shuffling: combining DVFS and thread migration to reduce energy consumptions for multi-core systems

Author
Cai, Q.; González, J.; Magklis, G.; Chaparro, P.; Gonzalez, A.
Type of activity
Presentation of work at congresses
Name of edition
International Symposium on Low Power Electronics and Design 2011
Date of publication
2011
Presentation's date
2011-08-01
Book of congress proceedings
International symposium on low power electronics and design: Fukuoka, Japan, August 1-3, 2011
First page
379
Last page
384
DOI
https://doi.org/10.1109/ISLPED.2011.5993670 Open in new window
URL
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5993670 Open in new window
Abstract
In recent years, multi-core systems have become mainstream in computer industry. The design of multi-cores takes advantage of thread-level parallelism in emerging applications that are computationally intensive and highly parallel. Energy efficiency is one of the biggest challenges in the design of multi-core systems, and workload imbalance among parallel threads is one of sources of energy inefficiency. Many techniques based on dynamic voltage frequency scaling (DVFS) are proposed to save energ...
Keywords
DVFS, Multi-core, SMT, Thread migration, Thread shuffling
Group of research
ARCO - Microarchitecture and Compilers

Participants

  • Cai, Qiong  (author and speaker )
  • González González, José  (author and speaker )
  • Magklis, Grigorios  (author and speaker )
  • Chaparro, Pedro  (author and speaker )
  • Gonzalez Colas, Antonio Maria  (author and speaker )