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Reusing cached schedules in an out-of-order processor with in-order issue logic

Author
Palomar, O.
Type of activity
Theses
Other related units
Department of Computer Architecture
Defense's date
2011-05-09
URL
http://hdl.handle.net/2117/94564 Open in new window
Abstract
Modern processors use out-of-order processing logic to achieve high performance in Instructions Per Cycle (IPC) but this logic has a serious impact on the achievable frequency. In order to get better performance out of smaller transistors there is a trend to increase the number of cores per die instead of making the cores themselves bigger. Moreover, for throughput-oriented and server workloads, simpler in-order processors that allow more cores per die and higher design frequencies are becoming ...
Group of research
CAP - High Performace Computing Group
Citation
Palomar Pérez, Ó. "Reusing cached schedules in an out-of-order processor with in-order issue logic". Tesi doctoral, UPC, Departament d'Arquitectura de Computadors, 2011.

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