Loading...
Loading...

Go to the content (press return)

TARCAD: a template architecture for reconfigurable accelerator designs

Author
Shafiq, M.; Pericas, M.; Navarro, Nacho; Ayguade, E.
Type of activity
Presentation of work at congresses
Name of edition
9th IEEE Symposium on Application Specific Processors
Date of publication
2011
Presentation's date
2011-06-05
Book of congress proceedings
Proceedings of the 2011 IEEE 9th Symposium on application specific processors (SASP): 5-6 June 2011, San Diego, CA, USA
First page
8
Last page
15
DOI
https://doi.org/10.1109/SASP.2011.5941071 Open in new window
URL
http://ieeexplore.ieee.org/search/srchabstract.jsp?tp=&arnumber=5941071&openedRefinements%3D*%26filter%3DAND%28NOT%284283010803%29%29%26searchField%3DSearch+All%26queryText%3DTARCAD%3A+A+Template+Architecture+for+Reconfigurable+Accelerator+Designs Open in new window
Keywords
Computer architecture, Field programmable gate arrays, Hardware design languages, Kernel, Layout, Monitoring, Registers
Group of research
CAP - High Performace Computing Group

Participants

  • Shafiq, Muhammad  (author and speaker )
  • Pericas Gleim, Miquel  (author and speaker )
  • Navarro, Nacho  (author and speaker )
  • Ayguade Parra, Eduard  (author and speaker )