Loading...
Loading...

Go to the content (press return)

Vectorized register tiling

Author
Berna, A.; Jimenez, M.; Llaberia, J.
Type of activity
Report
Date
2012-01
Code
UPC-DAC-RR-CAP-2012-4
Repository
http://hdl.handle.net/2117/16308 Open in new window
URL
https://www.ac.upc.edu/app/research-reports/html/2012/5/abstractAndPoster.pdf Open in new window
Abstract
In the last years, there has been much effort in commercial compilers (icc, gcc) to exploit efficiently the SIMD capabilities and the memory hierarchy that the current processors offer. However, the small numbers of compilers that can automatically exploit these characteristics achieve in most cases unsatisfactory results. Therefore, the programmers often need to apply by hand the optimizations to the source code, write manually the code in assembly or use compiler built-in functions (such intri...
Citation
Berna, A.; Jimenez, M.; Llaberia, J. "Vectorized register tiling". 2012.
Group of research
CAP - High Performace Computing Group

Participants

Attachments