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Armejach Sanosa, Adria

Total activity: 19

Scientific and technological production

1 to 19 of 19 results
 
  • UPC-High Performance Computing VIII

     Ayguade, E.; Torres, J.; Llaberia, J.; Morancho, E.; Monreal, T.; Martorell, X.; Cortes, A.; Corbalan, J.; Gil, Marisa; Jimenez, D.; Becerra, Y.; Utrera, G.; Tous, R.; Herrero, J.; Guitart, J.; Gonzalez, M.; Alvarez, C.; Gimenez, J.; Moreto, M.; Armejach, A.; Alvarez, L.; Korakitis, O.; Bosch, J.
    Competitive project
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  • Using Arm’s scalable vector extension on stencil codes  Open access

     Armejach, A.; Caminal, H.; Cebrián González, Juan Manuel; Langarita, R.; González-Alberquilla, R.; Adeniyi-Jones, C.; Valero, M.; Casas, M.; Moreto, M.
    Journal of supercomputing
    Vol. 76, p. 2039-2062
    DOI: 10.1007/s11227-019-02842-5
    Date of publication: 2020-03
    Journal article
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  • Ajut complementari IJCI-2017-33945

     Armejach, A.
    Competitive project
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  • Design trade-offs for emerging HPC processors based on mobile market technology  Open access

     Armejach, A.; Casas, M.; Moreto, M.
    Journal of supercomputing
    Vol. 75, num. 9, p. 5717-5740
    DOI: 10.1007/s11227-019-02819-4
    Date of publication: 2019-09-01
    Journal article
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  • Stencil codes on a vector length agnostic architecture  Open access

     Armejach, A.; Caminal, H.; Cebrián González, Juan Manuel; González-Alberquilla, R.; Adeniyi-Jones, C.; Valero, M.; Casas, M.; Moreto, M.
    International Conference on Parallel Architectures and Compilation Techniques
    p. 1-12
    DOI: 10.1145/3243176.3243192
    Presentation's date: 2018-11-01
    Presentation of work at congresses
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  • Arquitectura de Computadors d'Altes Prestacions

     Valero, M.; Moreto, M.; Armejach, A.; Alvarez, L.; Llaberia, J.; Morancho, E.; Monreal, T.; Fernandez, A.; Llosa, J.; Gonzalez, M.
    Competitive project
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  • MUSA: a multi-level simulation approach for next-generation HPC machines

     Grass, T.; Allande, C.; Armejach, A.; Rico, A.; Ayguade, E.; Labarta, J.; Valero, M.; Casas, M.; Moreto, M.
    International Conference for High Performance Computing, Networking, Storage and Analysis
    p. 1-12
    Presentation's date: 2016-11-13
    Presentation of work at congresses
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  • Computacion de Altas Prestaciones VII

     Ayguade, E.; Valero, M.; Torres, J.; Labarta, J.; Llaberia, J.; Corbalan, J.; Morancho, E.; Fernandez, A.; Cortes, A.; Monreal, T.; Gil, Marisa; Becerra, Y.; Jimenez, D.; Herrero, J.; Alvarez, C.; Gonzalez, M.; Guitart, J.; Utrera, G.; Tous, R.; Carrera, D.; Badia, R.M.; Moreto, M.; Gimenez, J.; Morillo, J.; Armejach, A.; Alvarez, L.; Martorell, X.; Llosa, J.
    Competitive project
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  • Commit on overflow  Open access

     Stipic, S.; Armejach, A.; Unsal, O.; Cristal, A.; Valero, M.
    Date: 2014
    Report
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  • An empirical evaluation of High-Level Synthesis languages and tools for database acceleration  Open access

     Arcas Abella, Oriol; Ndu, G.; Sonmez, N.; Ghasempour, M.; Armejach, A.; Navaridas, J.; Song, W.; Mawer, J.; Cristal, A.; Lujan, Mikel
    International Conference on Field Programmable Logic and Applications
    p. 1-8
    DOI: 10.1109/FPL.2014.6927484
    Presentation of work at congresses
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  • Techniques to improve performance in requester-wins hardware transactional memory

     Armejach, A.; Titos, R.; Negi, A.; Unsal, O.; Cristal, A.
    ACM transactions on architecture and code optimization
    Vol. 10, num. 4, p. 1-25
    DOI: 10.1145/2555289.2555299
    Date of publication: 2013-12
    Journal article
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  • Computación de Altas Prestaciones VI

     Valero, M.; Guitart, J.; Monreal, T.; Herrero, J.; Ayguade, E.; Labarta, J.; Badia, R.M.; Martorell, X.; Jimenez, D.; Alvarez, C.; Maric, B.; Rajovic, N.; Pavlovic, M.; Rico, A.; Puzovic, N.; Gelado, I.; Sancho, J.C.; Smiljkovic, V.; Nou, R.; Gimenez, J.; Yazdanpanah, F.; Moreto, M.; Verdu, J.; Planas, J.; Gayatri, R.; Berna, A.; Kestor, G.; Fitó, O.; Kosmidis, L.; Alvanos, M.; Ferrer, R.; Duran, A.; Bueno, J.; Macias, M.; Grass, T.; Beltran, V.; Polo, J.; Garcia, M.; Llosa, J.; Corbalan, J.; Gil, Marisa; Torres, J.; Sánchez-Carracedo, F.; Alex Ramirez; Olive, A.; Jimenez, M.; Fernandez, A.; Cortes, A.; Navarro, J.; Llaberia, J.; Navarro, N.; Jokanovic, A.; Poggi, N.; Sanchez, F.; Becerra, Y.; Carrera, D.; Gonzalez, M.; Morancho, E.; Pajuelo, M.A.; Costa, J.; Pérez, J.; Cristal, A.; González, J.; Marti, J.; Gioiosa, R.; Duric, M.; Stanic, M.; Sonmez, N.; Hussain, T.; Gajinov, V.; Tomic, S.; Arcas Abella, Oriol; Stipic, S.; Karakostas, V.; Hayes, T.; Armejach, A.; Yalcin, G.; Nemirovsky, D.; Bertran, R.; Alvarez, Ll.; Morari, A.; Subotic, V.; Seyedi, A.; Jorda, M.; Giralt, J.; Jalle, J.; Milic, U.; Tanasic, I.; Utrera, G.; Casas, M.; Tous, R.; Villalba, Á.; Brugger, M.; Cazorla, F. J.; Jaulmes, L.; Quiñones, E.; Elangovan, V.; Ejarque, J.; Bellens, P.; Sirvent, R.; Lezzi, D.; Liu, Q.; Radojkovic, P.; Panic, M.; Cakarevic, V.; Abella, J.; Ciesko, J.; Tejedor, E.; Cabezas, J.; Roca, D.; Allande, C.; Marjanovic, V.; Ratkovic, I.; Servat, H.; Vilanova, L.; Llort, G.; Unsal, O.; Markovic, N.; Jiménez, V.; Garcia, V.; Reig, G.; Miranda, A.; Farreras, M.; Artiaga, E.; Teruel, J.; Caballero, D.; Subirats, J.
    Competitive project
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  • Novel SRAM bias control circuits for a low power L1 data cache

     Seyedi, A.; Armejach, A.; Cristal, A.; Unsal, O.; Valero, M.
    NORCHIP Conference: the Nordic Microelectronics Event
    p. 1-6
    DOI: 10.1109/NORCHP.2012.6403113
    Presentation's date: 2012-11
    Presentation of work at congresses
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  • Circuit design of a dual-versioning L1 data cache

     Seyedi, A.; Armejach, A.; Cristal, A.; Unsal, O.; Hur, I.; Valero, M.
    Integration. The VLSI journal
    Vol. 45, num. 3, p. 237-245
    DOI: 10.1016/j.vlsi.2011.11.015
    Date of publication: 2012-06
    Journal article
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  • Using a reconfigurable L1 data cache for efficient version management in hardware transactional memory

     Armejach, A.; Seyedi, A.; Titos, R.; Hur, I.; Cristal, A.; Unsal, O.; Valero, M.
    International Conference on Parallel Architectures and Compilation Techniques
    p. 361-371
    DOI: 10.1109/PACT.2011.67
    Presentation's date: 2011-10
    Presentation of work at congresses
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  • Circuit design of a dual-versioning L1 data cache for optimistic concurrency

     Seyedi, A.; Armejach, A.; Cristal, A.; Unsal, O.; Hur, I.; Valero, M.
    Great Lakes Symposium on VLSI
    p. 325-330
    DOI: 10.1145/1973009.1973074
    Presentation's date: 2011-05
    Presentation of work at congresses
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  • Circuit design of a dual-versioning L1 data cache for optimistic concurrency  Open access

     Seyedi, A.; Armejach, A.; Cristal, A.; Unsal, O.; Hur, I.; Valero, M.
    Date: 2011
    Report
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  • ShadowHTM: Using a dual-bitcell L1 data cache to improve hardware transactional memory performance

     Armejach, A.; Seyedi, A.; Titos, R.; Hur, I.; Unsal, O.; Cristal, A.; Valero, M.
    Date: 2010
    Report
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  • EazyHTM: EAger-LaZY hardware transactional memory

     Tomic, S.; Perfumo, C.; Kulkami, C.; Armejach, A.; Cristal, A.; Unsal, O.; Harris, T.; Valero, M.
    Annual IEEE/ACM International Symposium on Microarchitecture
    p. 145-155
    Presentation's date: 2009-12
    Presentation of work at congresses
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